A bus architecture of a computer system conveys much of the information and signals involved in the computer system's operation. In a typical computer system, one or more buses are used to connect a central processing unit (CPU) to a memory and to input/output devices so that data and control signals can be readily transmitted between these different components. When the computer system executes its programming, it is imperative that data and information flow as fast as possible in order to make the computer system as responsive as possible to the user. With many peripheral devices and subsystems, such as graphics adapters, full motion video adapters, small computer systems interface (SCSI) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. These applications are just some examples of peripheral devices and subsystems which benefit substantially from a very fast bus transfer rate.
Much of the computer system's functionality and usefulness to a user is derived from the functionality of the peripheral devices. For example, the speed and responsiveness of the graphics adapter is a major factor in a computer system's usefulness as an entertainment device. Or, for example, the speed with which video files can be retrieved from a hard drive and played by the graphics adapter determines the computer system's usefulness as a training aid. Hence, the rate at which data can be transferred among the various peripheral devices often determines whether the computer system is suited for a particular purpose.
The electronics industry has, over time, developed several types of bus architectures. Recently, the PCI (peripheral component interconnect) bus architecture has become one of the most widely used and widely supported bus architectures in the industry. The PCI bus was developed to provide a high speed, low latency bus architecture from which a large variety of systems could be developed.
Prior Art FIG. 1 shows a typical PCI bus architecture 100. PCI bus architecture 100 is comprised of CPU 102 and host memory 104, coupled to PCI-to-host bridge 106 through CPU local bus 108 and memory bus 110, respectively. PCI-to-host bridge 106 is a bi-directional bridge (e.g., a PCI-to-host bridge and a host-to-PCI bridge). PCI bus 112 is coupled to each of PCI initiator devices 114, 116, 118, 120, 122, 124, respectively, and is also coupled to an arbiter (not shown) in PCI-to-host bridge 106.
Referring still to Prior Art FIG. 1, each of PCI initiator devices 114, 116, 118, 120, 122, 124 (hereafter, PCI initiators 114-124) use PCI bus 112 to transmit and receive data. PCI bus 112 is comprised of functional signal lines, for example, interface control lines, address/data lines, error signal lines, and the like. Each of PCI initiators 114-124 are coupled to the functional signal lines comprising PCI bus 112. When one of PCI initiators 114-124 requires the use of PCI bus 112 to transmit or receive data (e.g., a write transaction or a read transaction, respectively), it requests PCI bus ownership from PCI-to-host bridge 106. Upon being granted ownership of PCI bus 112, the PCI initiator device (e.g., PCI initiators 114-124) carries out its respective transaction.
Each of PCI initiators 114-124 may independently request ownership of PCI bus 112. Thus, at any given time, several of PCI initiators 114-124 may be requesting PCI bus ownership simultaneously. Where there are simultaneous requests for ownership of PCI bus 112, PCI-to-host bridge 106 arbitrates between requesting PCI initiators to determine which requesting PCI initiator is to be granted PCI bus ownership. When one of PCI initiators 114-124 is granted ownership of PCI bus 112, it initiates its read or write transaction with a host target device (e.g., host memory 104). When the data transaction is complete, the PCI initiator relinquishes ownership of PCI bus 112, allowing PCI-to-host bridge 106 to reassign PCI bus 112 to another requesting PCI initiator.
Thus, only one data transaction can take place on PCI bus 112 at any given time. In order to maximize the efficiency and data transfer bandwidth of PCI bus 112, PCI initiators 114-124 follow a definitive set of protocols and rules. These protocols are designed to standardize the method of accessing, utilizing, and relinquishing PCI bus 112, so as to maximize its data transfer bandwidth.
With reference now to Prior Art FIG. 2, a typical PCI-to-host bridge design (e.g., PCI-to-host bridge 106) is illustrated. PCI-to-host bridge 106 includes host master 211, data first-in first out (FIFOs) 212, and PCI target 214. PCI-to-host bridge 106 is a bi-directional bridge coupled between host bus 210 and PCI bus 112 (for simplicity, the host-to-PCI portion of the bridge is not shown). Host bus 210 is a bus conforming to any type of protocol.
In the prior art, for a read transaction between a PCI initiator device (e.g., PCI initiator 124) and host memory 104 via PCI-to-host bridge 106, PCI initiator 124 requests and is granted ownership of PCI bus 112 as described above. To access PCI-to-host bridge 106, PCI initiator 124 identifies the bridge by its address, and the bridge (specifically, PCI target 214) recognizes its address and asserts a claim to the access. PCI target 214 in PCI-to-host bridge 106 recognizes that time will be needed to complete this read transaction (the time is needed for host master 211 to claim access to host bus 210, then the requested data are retrieved from host memory 104, and the requested data are returned to and stored in data FIFOs 212). Thus, PCI-to-host bridge 106 immediately retries PCI initiator 124 (that is, PCI-to-host bridge 106 terminates the access to PCI initiator 124), thereby freeing up PCI bus 112 for use by another PCI initiator.
Continuing with Prior Art FIG. 2, while access to host memory 104 continues to proceed in order to retrieve the requested data, PCI initiator 124 retries the access to PCI-to-host bridge 106 (that is, PCI initiator attempts to re-establish the access to PCI target 214 as described above). This retry occurs almost immediately (typically after two clock cycles) after the access is terminated by PCI-to-host bridge 106. PCI-to-host bridge 106 again claims the access and checks data FIFOs 212 to see if the data from host memory 104 have been retrieved. If not, PCI-to-host bridge 106 again retries the access (again terminating the access to PCI initiator 124). This process continues until data are present in data FIFOs 212, at which time the data are read to PCI initiator 124 and the read transaction is completed.
The prior art process described above is problematic because of the number and frequency of retries between PCI initiator 124 and PCI-to-host bridge 106 that occur after the read transaction is initiated until the data are ready to be forwarded from the data FIFOs. During each of these retries, no data are being transferred to PCI initiator 124. In addition, each of these interactions requires ownership of the PCI bus for the period of time needed to complete each interaction, and thus during those periods of time the PCI bus is not available for other PCI devices to initiate transactions or receive data. Thus, in the prior art, nonproductive interactions in which no data are transferred consume a portion of the computer system's bandwidth, and delays are caused to other devices while PCI initiator 124 and PCI-to-host bridge 106 take turns retrying accesses.
In addition, the prior art is problematic because PCI initiator 124 must arbitrate for control of PCI bus 112 prior to each retry, since control of the PCI bus was relinquished when PCI-to-host bridge 106 retried (terminated) the access. Since other transactions initiated by other PCI initiator devices on PCI bus 112 will also be underway, and due to the time needed for the arbitration process, PCI initiator 124 generally will encounter a delay before it is again granted control of PCI bus 112. In the meantime, while PCI initiator 124 is attempting to assert access to PCI-to-host bridge 106, the data sought by PCI initiator 124 have probably already been delivered into data FIFOs 212 from host memory 104. However, PCI initiator 124 is not able to obtain these data until bus arbitration is complete and access is again obtained to PCI-to-host bridge 106. Thus, another disadvantage to the prior art is that transactions are delayed and data transfer is held up because of the regular and arbitrary access retries.
The disadvantages of the prior art are multiplied by the fact that there are more than one PCI initiator devices in a computer system, each PCI initiator device also encountering the same problems as those described above. Thus, in the prior art, a significant number of clock cycles are lost to arbitrating the PCI bus and retrying accesses, and to the consequential delay in data delivery. Hence, in the prior art, the functionality of the computer system and the total data transfer bandwidth of the computer system are diminished.
Accordingly, what is needed is a method and/or system which minimizes the unnecessary access retries between the initiator device and the bus bridge device. What is also needed is a system and/or method that addresses the above need and also reduces the consequences of repeated access attempts, so that the computer system's bandwidth is more optimally utilized. What is further needed is a system and/or method that addresses the above needs and also expedites the delivery of requested data from the bus bridge device to the initiator device. The present invention provides a novel solution to the above needs.
These and other objects and advantages of the present invention will become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.